Digital Logic
FPGA implementations, hardware description languages, state machines, timing constraints, and structural models.
Registers & 7-Segment Calculator
Implementing n-bit registers and multiplexers to control data flow into a universal 7-segment display for a calculator circuit.
Multiply FSM & Accumulator
Designing a multiplying finite state machine using an accumulator, shift register, and Moore/Mealy outputs.
Clock Dividers & D Flip-Flops
Constructing clock dividers and D Flip-Flops using asynchronous registers to configure LED flash rates.
LED Shift Register
Building an LED shifter using custom shift registers and clock dividers to create sequential lighting patterns.
Mealy & Moore Sequence Detectors
Creating overlapping and non-overlapping sequence detectors using Moore and Mealy finite state machines, including transition diagrams.
Propagation Delay & Glitches
Analyzing combinational logic circuits to observe and simulate propagation delays and logic circuit glitches.
Multiplexers & Priority Encoders
Supplementary Verilog lab focusing on the structural modeling and simulation of multiplexers, 3-to-8 decoders, and priority encoders.